1. Technical Field
Embodiments relate to a phase detector, a phase-frequency detector, and a digital phase locked loop, and more particularly, to a phase detector and a phase-frequency detector in which output timing is controlled according to a control signal and a digital phase locked loop including the same.
2. Related Art
Research has been conducted to develop a digital phase locked loop for use in place of an analog phase locked loop. A conventional digital phase locked loop (DPLL) may include a time digital converter (TDC). A bang-bang type phase detector may be used to reduce power consumption.
Because the bang-bang type phase detector has a nonlinear gain characteristic, the gain of the bang-bang type phase detector is likely to change according to a jitter of an inputted reference clock signal. As a result, the bandwidth of the entire phase locked loop is likely to change.
FIG. 1a shows a conventional DPLL 1. The conventional DPLL 1 includes a bang-bang type phase detector (BB-PD) 20, a filter 40, a digital control oscillator (DCO) 50, and a feedback circuit 60.
The conventional DPLL 1 using the BB-PD 20 includes an initialization circuit (not shown) to determine an initial frequency of an output signal of the DCO 50, and the initialization circuit provides an initialization signal init to the DCO 50. The initial frequency of the output signal of the DCO 50 may be similar to a frequency of a reference clock signal Clk_ref which is inputted for locking.
The conventional DPLL 1 further includes a delay controller 10 and a delay line 70 and thereby controls the addition of jitter to the reference clock signal Clk_ref, whereby the gain of the BB-PD 20 may be controlled and the bandwidth of the DPLL 1 may be maintained. The delay controller 10 outputs a control signal dcon according to the reference clock signal Clk_ref and a delay control signal DCS, thereby controlling the delay of the delay line 70.
FIG. 1b is a block diagram showing the BB-PD 20 of FIG. 1a. The conventional BB-PD 20 uses a D-type flip-flop (DFF) to determine the lead and lag of the reference clock signal Clk_ref relative to a feedback frequency signal Clk_fb.
FIG. 2a shows a conventional DPLL 1′ which uses a bang-bang type phase-frequency detector (BB-PFD) 30 instead of the BB-PD 20 shown in FIG. 1a. Unlike the conventional DPLL 1 that uses the BB-PD 20, the conventional DPLL 1′ which uses the BB-PFD 30 does not need an initialization circuit for setting an initial frequency of a DCO 50′. However, the operational principle of the conventional DPLL 1′ is substantially the same as that of the conventional DPLL 1 shown in FIG. 1a. 
FIG. 2b shows the detailed structure of the BB-PFD 30 of FIG. 2a. The BB-PFD 30 uses a D-type flip-flop 20 to determine the lead and the lag of a reference clock signal Clk_ref′ relative to the feedback frequency signal Clk_fb.
Because each of the conventional DPLLs 1 and 1′ uses the delay line 70 to add jitter to a reference clock signal in order to maintain a constant bandwidth while using the BB-PD 20 or the BB-PFD 30, a circuit area and power consumption are increased due to the presence of the delay line 70.